Manish Patel

ASIC Verification skills:
-> Experience of verification taking several chips from specification to tapeout
-> Expertise with SV and UVM based Verification 
-> Analog & Mixed signal design and digital Verification
->Testbench implementation using SystemVerilog and UVM 
-> Ability to modify or develop checkers, monitors, etc. from scratch.
-> Exposure to simulation-based verification, assertions/SVA, functional coverage and regression management.
-> Ability to debug Testbench and RTL issues and handle legacy Testbench and make enhancements
->Verification using Constraint Random Generation
-> Coverage Driven Verification
-> Understanding of standard ASIC Verification techniques .. Test Planning, Testbench creation, code, and functional coverage, Directed and Constrained random stimulus and test generation, Assertion based flow,
-> UVM Register Modeling 
-> Regression setup using vManager, Bug/PRCR Reporting, and PRCR closure, Jira, Collabonet 
-> Protocols: AMBA(APB,AHB,AXI), USB 2.0 CORE ,UART, I2C,SPI,DVS,DFI,GDDR6/7
-> Version control : DesignSync,Perforce

Power electronics: power Converter, converter control, Converter Circuits. PFC+LLC combo converter controller IC.LLC Converter 
 

• 3 years of professional experience in pre-silicon Design Verification. 
• 2 years of experience working with NXP Semiconductor, Netherlands as a verification engineer (Contractor)
• Experience in Testbench implementation using System Verilog and UVM. 
• Ability to modify existing env. and develop checkers, monitors, and predictors from scratch.
• Exposure to simulation-based verification, assertions/SVA, functional coverage,

Regression management using Cadence vManager, Repository management (Design sync & Perforce)

• Ability to debug Testbench and RTL issues and make enhancements in legacy Testbench
• Directed and Constrained random test cases and stimulus test generation 
• Configured, customized, and connected Universal Verification Components in the UVM Verification environment 
• Created system-level sequences to drive stimulus patterns into a DUT
• Experience in (AC-DC and DC-DC converter) Mixed-signal design & digital verification
• Contributed 4 verification IP projects for successful tape-out

M.E in VLSI & Embedded System design   -2011-13

B.E ELECTRONICS & COMMUNICATION- 2007-2011